Electrically erasable and programmable read only memories (EEPROMs) are widely used in computer systems for storing data. The typical data storage element of an EEPROM is a floating gate transistor, which is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source and drain regions. Data is represented by charge stored on the floating gate and the resulting conductivity obtained between source and drain regions.
For example, a floating gate memory cell can be formed in a P-type substrate with an N-type diffused source region and an N-type drain diffusion formed in the substrate. The spaced apart source and drain regions define an intermediate channel region. A floating gate, typically made of doped polysilicon, is located over the channel region and is electrically isolated from the other cell elements by oxide. For example, a thin gate oxide can be located between the floating gate and the channel region. A control gate is located over the floating gate and can also be made of doped polysilicon. The control gate is separated from the floating gate by a dielectric layer.
Flash memories typically have an array of non-volatile memory cells that are arranged in addressable blocks. The memory cells can be individually programmed, but are usually erased as a whole block. That is, any charge stored on the floating gate of a block of memory cells is removed using a common erase process. The process can be complex and time consuming. In a typical flash erase operation, a block of memory cells typically are first programmed to a high threshold voltage (placing charge on floating gate). Electrical erase pulses are then applied to the memory cells to remove the stored charges. A verification operation determines if the memory cells have a low threshold state (erased state). For the memory cells in the block that are in an over-erased condition, a procedure is implemented to raise the threshold voltage of over-erased cells. The erase operation, therefore, has multiple steps that require time and relatively complex circuitry.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory that can be erased using a simpler procedure.
The above-mentioned problems with memory devices and memory erase operations and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a non-volatile memory device comprises an array of non-volatile memory cells, and control circuitry coupled to the array. The control circuitry performs an erase operation on the non-volatile memory cells. The erase operation consists of applying one or more erase pulses to the memory cells and performing a convergence operation to recover over-erased memory cells.
In a first embodiment, the non-volatile memory cells are floating gate transistors and the convergence operation comprises biasing a source region of the memory cells to ground potential and biasing a substrate body of the memory cells to negative potential. A positive voltage pulse having a predetermined duration and an upper voltage level is applied to a drain region of the memory cells, and a ramped voltage signal is applied to a control gate.
In a second embodiment, the non-volatile memory cells are floating gate transistors and the convergence operation comprises biasing a substrate body of the memory cells to ground potential and biasing a drain region of the memory cells to a positive potential, and applying a ramped voltage signal to a control gate.
In yet another embodiment, the non-volatile memory cells are floating gate transistors and the convergence operation comprises biasing a substrate body of the memory cells to ground potential and biasing a drain region of the memory cells to a first positive potential, biasing a control gate of the memory cells to a second positive potential, and applying a ramped voltage signal to a source region of the memory cells.
A method of erasing a block non-volatile memory cells comprises applying an erase voltage configuration to the block of floating gate transistor memory cells comprising source and drain regions, a channel formed in a body of the transistor between the source and drain regions, a floating gate, and a control gate. A convergence operation is performed on the block of memory cells to adjust memory cells that are over-erased during the application of the erase voltage configuration. The convergence operation comprises biasing the source region of the memory cells to ground potential, biasing the body to a negative potential, applying a positive voltage pulse having a predetermined duration in the range of 10 xcexcs to 100 ms and an upper voltage level in a range of 2.5 to 5 volts to the drain region, and applying a ramped voltage signal having a duration in a range of 10 xcexcs to 100 ms, a final voltage in a range of 0 to 4 volts, and an initial voltage in a range of xe2x88x922 to 0 volts to the control gate.
A method of erasing a block non-volatile memory cells comprises applying an erase voltage configuration to the block of floating gate transistor memory cells comprising source and drain regions, a channel formed in a body of the transistor between the source and drain regions, a floating gate, and a control gate. A convergence operation is performed on the block of memory cells to adjust memory cells that are over-erased during the application of the erase voltage configuration. The convergence operation comprises floating the source region of the memory cells, biasing the body to ground, applying a voltage in a range of 6 to 9 volts to the drain region, and applying a ramped voltage signal having a duration in a range of 10 xcexcs to 100 ms, a final voltage in a range of 1 to 4 volts, and an initial voltage of about 0 volts to the control gate.
A method of erasing a block non-volatile memory cells comprises applying an erase voltage configuration to the block of floating gate transistor memory cells comprising source and drain regions, a channel formed in a body of the transistor between the source and drain regions, a floating gate, and a control gate. A convergence operation is performed on the block of memory cells to adjust memory cells that are over-erased during the application of the erase voltage configuration. The convergence operation comprises floating the source region of the memory cells, biasing the body to ground, applying a voltage in a range of 6 to 9 volts to the drain region, and applying a voltage in a range of 0.5 to 3 volts to the control gate.
A method of erasing a block non-volatile memory cells comprises applying an erase voltage configuration to the block of floating gate transistor memory cells comprising source and drain regions, a channel formed in a body of the transistor between the source and drain regions, a floating gate, and a control gate. A convergence operation is performed on the block of memory cells to adjust memory cells that are over-erased during the application of the erase voltage configuration, the convergence operation comprises biasing the body to ground, applying a constant voltage in a range of 2 to 5 volts to the control gate, applying another constant voltage in the range of 3-6 volts to the drain, and applying a ramped voltage signal having a duration in a range of 10 xcexcs to 100 ms, a final voltage of about 0 volts, and an initial voltage in a range of 2 to 5 volts to the source region.
Other embodiments of the present invention are described herein. The above summary is not intended to cover all aspects of the present invention and the present invention is provided in the claims.